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ks 88c0716/p0716 product overview 1- 1 1 product overview sam8 product family samsung's sam8 7 family of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. important cpu features include: ? efficient register-oriented architecture ? selectable cpu clock sources ? idle and stop power-down mode release by interrupt ? built-in basic timer with watchdog function a sophisticated interrupt structure recognizes up to eight interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum of six cpu clocks) can be assigned to specific interrupt levels. ks 88c0716/p0716 microcontroller s ks 88c0716/p0716 single-chip 8-bit microcontroller s are based on the powerful sam8 7 cpu architecture. the internal register file is logically expanded to increase the on-chip register space. the ks88c0716 has 16-kbyte mask-programmable rom. the KS88P0716 has 16-kbyte one-time-programmable eprom. following samsung's modular design approach, the following peripherals are integrated with the sam8 7 core: ? seven programmable i/o ports (total 56 pins) ? one 8-bit bas ic timer for oscillation stabilization and watchdog functions ? one synchronous operating mode and three full -duplex asynchronous uart modes ? t wo 8-bit timers with interval timer and pwm modes ? two 16-bit general-purpose timer/counters otp the ks88c0716 microcontroller is also available in otp (one time programmable) version, KS88P0716. KS88P0716 microcontroller has an on-chip 16-kbyte one-time-programmable eprom instead of masked rom. the KS88P0716 is comparable to ks88c0716, both in function and in pin configuration.
product overview ks 88c0716/p0716 1- 2 features cpu ? sam8 7 cpu core memory ? 272-byte general purpose register area ? 16-kbyte internal program memory ? rom-less operating mode external interface ? 64-kbyte external data memory area ? 64-kbyte external program memory area (rom- less mode) instruction set ? 78instructions ? idle and stop instruct ions for power-down mode instruction execution time ? 500 ns at 12 mhz f cpu ( m in.) interrupts ? 17 interrupt s ources ? 17 interrupt vectors ? eight interrupt levels ? fast interrupt processing general i/o ? four nibble-programmable ports ? one bit-programmable port ? two bit-programmabl e ports for external interrupts timers ? two 8-bit timers with interval timer and pwm modes timer/counters ? two 16-bit general-purpose timer/counters basic timer ? one 8-bit basic timer (bt) for oscillation stabilization control and watch dog timer function. serial port ? one synchronous operating mode and three full- duplex asynchronous uart modes operating temperature range ? ? 4 0 c to + 85 c operating voltage range ? 2.7 v to 5.5 v package types ? 64-pin sdip, 64-pin qfp
ks 88c0716/p0716 product overview 1- 3 table 1-1. comparison table feature ks88c0116 ks88c0716 core sam8 sam87 rom 16 k bytes same ram 272 bytes same i/o 54 56 (add two pins) port 6 open drain (9 v drive) normal c-mos output i/o option none same timer 8-bit back-up timer none timer a, b ? 8-bit ? interval/pwm mode ? timer a match interrupt same (some differ in interval mode, see manual) timer c, d ? gate function ? timer/counter same watchdog timer none watchdog timer (with bt) sio uart ? 8-bit/9-bit uart ? sio same interrupt external 12 ? p2.4?p2.7, p4.0?p4.7 same internal 6 ? timer a, c, d, si, so, back-up internal 5 ? timer a, c, d, si, so power down stop/idle same oscillator crystal, ceramic same cpu clock divider 1/2 1/1, 1/2, 1/8, 1/16 execution time (min.) 0.6 m s at 20 mhz (f cpu = 10 mhz) 0.5 m s at 12 mhz (f cpu = 12 mhz) operating frequency max. 20 mhz (f cpu = 10 mhz) max. 12 mhz (at 4.5 v) (2) max. 4 mhz (at 2.7 v) operating voltage 4.5?5.5 v 2.7?5.5 v at 4 mhz 4.5?5.5 v at 12 mhz otp/mtp mtp otp pin assignment ? different package 64sdip/64qfp same start address 0020h 0100h p5con, p6con bank0 bank1 interrupt pending bit clear write "1" write "0" notes: 1. the ks88c0716 can replace the ks88c0116. their functions are mostly the same, but there are some differences. table 1-1 shows the comparison of ks88c0716 and ks88c0116.
product overview ks 88c0716/p0716 1- 4 2. o perating frequency is maximum cpu clock; the maximum oscillation frequency is 22.1184 mhz. block diagram tcck tdck ta tb port i/o and interrupt control 16-kb rom 272-byte register file port 2 p2.0?p2.3, p2.4/int0?p2.7/int3 p3.0?p3.7 reset ea p5.0?p5.3 p5.4?p5.7 p6.0?p6.7 port 0 p0.0?p0.7 (a8?a15) port 1 p1.0?p1.7 (ad0?ad7) sam87 bus p4.0/int4 (tcg) p4.1/int5 (tdg) p4.2/int6? p4.7/int11 timers c and d port 3 port 4 port 5 port 6 x in x out basic timer main osc timers a and b serial port sam87 cpu rxd txd figure 1 -1 . ks88c0 7 16 block diagram
ks 88c0716/p0716 product overview 1- 5 ks88c0716 64-sdip (top view) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p0.7/a15 p1.0/ad0 p1.1/ad1 p1.2/ad2 p1.3/ad3 p1.4/ad4 p1.5/ad5 p1.6/ad6 p1.7/ad7 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 v dd2 v ss2 p2.0/ as p2.1/ ds p2.2/r/ w p2.3/ dm p2.4/int0/ wait p2.5/int1 p2.6/int2 p2.7/int3 p6.7 p6.6 p6.5 p6.4 p6.3 p6.2 p6.1 p0.6/a14 p0.5/a13 p0.4/a12 p0.3/a11 p0.2/a10 p0.1/a9 p0.0/a8 p4.7/int11 p4.6/int10 p4.5/int9 p4.4/int8 p4.3/int7 p4.2/int6 p4.1/int5/tdg p4.0/int4/tcg v dd 1 v ss1 x out x in ea p5.6 p5.7 reset p3.7/rxd p3.6/txd p3.5/tb p3.4/ta p3.3 p3.2 p3.1/tdck p3.0/tcck p6.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 figure 1- 2. ks88c0716 pin assignments (64-sdip)
product overview ks 88c0716/p0716 1- 6 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 52 53 54 55 56 57 58 59 60 61 62 63 64 p6.7 p6.6 p6.5 p6.4 p6.3 p6.2 p6.1 p6.0 p3.0/tcck p3.1/tdck p3.2 p3.3 p3.4/ta p1.5/ad5 p1.6/ad6 p1.7/ad7 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 v dd2 v ss 2 p2.0/ as p2.1/ ds p2.2/r/ w p2.3/ dm p2.4/int0/ wait p2.5/int1 p2.6/int2 p2.7/int3 p1.4/ad4 p1.3/ad3 p1.2/ad2 p1.1/ad1 p1.0/ad0 p0.7/a15 p0.6/a14 p0.5/a13 p0.4/a12 p0.3/a11 p0.2/a10 p0.1/a9 p0.0/a8 p4.7/int11 p4.6/int10 p4.5/int9 p4.4/int8 p4.3/int7 p4.2/int6 p4.1/int5/tdg p4.0/int4/tcg v dd1 v ss1 x out x in ea p5.6 p5.7 reset p3.7/rxd p3.6/txd p3.5/tb ks88c0716 64-qfp (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 figure 1- 3. ks88c0 7 16 pin assignments (64-qfp)
ks 88c0716/p0716 product overview 1- 7 table 1-2 . ks88c0 7 16 pin descriptions (64-sdip) pin name pin type pin description circuit number sdip pin number share pins p0.0 ? p0.7 i/o i/o port with nibble-programmable pins; i nput or push-pull, open-drain output and software assignable pull-ups; also configurable as external interface address lines a8 - a15. e 1?7, 64 a8 ? a15 p1.0 ? p1.7 i/o same general characteristics as port 0; also configurable as external interface address/data lines ad0 ? ad7. e 56?63 ad0 ? ad7 p2.0 ? p2.3 p2.4 ? p2.7 i/o i/o port with bit-programmable pins; i nput or push-pull output. lower nibble pins 0 ? 3 are configurable for external interface signals; upper nibble pins 4 ? 7 are bit- programmable for external interrupts int0 ? int3. p2.4 can also be used for external input. d-1 (lower nibble); d-1 (upper nibble; with noise filter) 40?47 as, ds, dm, r/ w int0 ? int3, wait p3.0 ? p3.7 i/o i/o port with bit-programmable pins; i nput or push-pull output. alternate functions include software- selectable uart transmit and receive on pins 3.7 and 3.6, timer b and timer a outputs at pins 3.5 and 3.4, and timer d and c clock inputs at pins 3.1 and 3.0. d-1 24? 31 tcck, tdck, ta, tb, txd, rxd p4.0 ? p4.7 i/o i/o port with bit-programmable pins; i nput or push-pull output; software- assignable pull-ups. alternate functions include external interrupt inputs int4 -i nt11 (with interrupt enable and pending control) and timer c and d gate input at p4.0 and p4.1. d (with noise filter) 8?15 int4 ? int11 , tcg, tdg p5.0 ?p5.7 i/o i/o port with nibble-programmable pins; i nput or push-pull, open-drain output; software- assignable pull-ups. e 21, 22, 50?55 ? p 6 .0 ? p 6 . 7 o output port with nibble-programmable pins; push-pull, open-drain output; software- assignable pull-ups. e-8 32?39 ? rxd i/o bi-directional serial data input pin ? 24 p3.7 txd i/o serial data output pin ? 25 p3.6 ta, tb i/o timer a and b output pins 4 27, 2 6 p3.4, p3.5 tcck, tdck i/o timer c and d external clock input pins d-1 30, 31 p3.0, p3.1 int0 ? int3 i/o external interrupts. i/o pin 2.4 (share pin with int0) is also configurable as a wait signal input pin for the external interface. d-1 (with noise filter) 40?43 p2.4 ? p2.7
product overview ks 88c0716/p0716 1- 8 table 1-2 . ks88c0 7 16 pin descriptions (continued) pin name pin type pin description circuit number sdip pin number share pins int4 ? int11 i/o bit-programmable external interrupt input pins with interrupt pending and enable /disable control d (with noise filter) 8?15 p4.0 ? p4.7 x in , x out ? system clock input and output pins ? 18, 19 ? reset i system reset pin (internal pull-up: 280 k w ) b 23 ? ea i external access (ea) pin with three modes: 0 v: normal operation (internal rom) 5 v: rom-less operation (external interface) ? 20 ? v dd2 , v ss2 ? power input pins for port output (external) ? 49, 48 ? v dd1 , v ss1 ? power input pins for cpu (internal) ? 16, 17 ?
ks 88c0716/p0716 product overview 1- 9 pin circuit data in/out pull-up enable in open-drain output disable v dd v dd pull-up resistor (typical value: 47 ) k w figure 1- 4. pin circuit type e (ports 0, 1, 5 ) data in/out pull-up enable v dd v ss v dd pull-up resistor (typical value: 47 ) k w open-drain figure 1-5 . pin circuit type e-8 (ports 6 )
product overview ks 88c0716/p0716 1- 10 data in/out in output disable v dd v ss port 2 (low byte) data external interface select ( as, ds, w, dm ) r/ m u x figure 1-6 . pin circuit type d-1 (p2.0 ? p2.3) in/out output disable v dd v ss external interrupt port 2 (high byte) data no rmal input or wait input noise filter figure 1-7 . pin circuit type d-1 (p2.4 ? p2.7)
ks 88c0716/p0716 product overview 1- 11 data in/out in output disable v dd v ss port 3 data control output select m u x figure 1-8 . pin circuit type d-1 (port 3) in/out output disable v dd v ss external interrpt input data input pull-up enable v dd noise filter pull-up resistor (typical value: 47 ) k w figure 1-9 . pin circuit type d (port 4)
product overview ks 88c0716/p0716 1- 12 reset v dd pull-up resistor (typical 210 k w) f igure 1- 10. pin circuit type b ( reset )
ks 88c0716/p0716 electrical data 1 4 - 1 14 electrical data overview in this section, ks 88c0716 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? d.c. electrical characteristics ? i/o capacitance ? a.c. electrical characteristics ? oscillation characteristics ? oscillation stabilization time
electrical data ks 88c0716/p0716 14 - 2 table 14- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? 0.3 to + 6.5 v input voltage v i all ports (in input mode) ? 0.3 to v dd + 0.3 output voltage v o all ports (in output mode) ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 10 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 ma total pin current for ports 0?4 + 100 total pin current for ports 5 and 6 + 100 operating temperature t a ? 4 0 to + 85 c storage temperature t stg ? 65 to + 150 c
ks 88c0716/p0716 electrical data 1 4 - 3 table 14-2 . d.c. electrical characteristics (t a = ? 4 0 c to + 85 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit input high voltage v ih1 all input pins except v ih2 0.8 v dd ? v dd v v ih2 x in v dd ? 0.5 input low voltage v il1 all input pins except v il2 ? ? 0.2 v dd v v il2 x in 0.4 output high voltage v oh1 v dd = 4.5 v to 5.5 v i oh = ? 4 ma port 5 , 6 v dd ? 1.0 ? ? v v oh2 v dd = 4.5 v to 5.5 v i oh = ? 1 ma all output pins except port 5 , 6 output low voltage v ol1 v dd = 4.5 v to 5.5 v i ol = 15 ma ports 5 and 6 ? ? 1.0 v v ol2 i ol = 2 ma ports 0 ?4 0.4 input high leakage current i lih1 v in = v dd all input pins except x in , x out ? ? 3 m a i lih2 v in = v dd , x in , x out 20 input low leakage current i lil1 v in = 0 v all input pins except x in , x out ? ? ? 3 m a i lil2 v in = 0 v , x in , x out ? 20 output high leakage current i loh v out = v dd all output pins ? ? 5 m a output low leakage current i lol v out = 0 v ? ? ? 5 m a pull-up resistor r l1 v in = 0 v; v dd = 5 v ports 0, 1, 4, 5 and 6 30 47 70 k w r l2 v in = 0 v; v dd = 5 v reset only 1 10 210 310
electrical data ks 88c0716/p0716 14 - 4 table 14-2 . d.c. electrical characteristics (continued) (t a = ? 4 0 c to + 85 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit supply current (1 ) i dd1 (2) v dd = 5 v 10% 12 -mhz oscillation ? 12 25 ma 4 -mhz oscillation 4.5 10 v dd = 3 v 10% 12 -mhz oscillation 6 15 4 -mhz oscillation 2.5 7 i dd2 (2) idle mode; v dd = 5 v 10% 12 -mhz oscillation 3 10 4 -mhz oscillation 1.5 4 idle mode; v dd = 3 v 10% 12 -mhz oscillation 1.2 3 4 -mhz oscillation 0.6 1.5 i dd3 stop mode: v dd = 5 v 10% 0.1 3 m a note s : 1. supply current does not include current drawn through internal pull-up resistors or external output current loads. 2. at supply current, the cpu clock frequency is same with oscillation frequency (cpu use non divided clock). table 14- 3. data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 2 ? 6 v data retention supply current i dddr stop mode, v dddr = 2.0 v ? ? 3 m a notes : 1. during the oscillator stabilization wait time (t wait ), all c pu operations must be stopped. 2. supply current does not include drawn through internal pull?up resistors and external output current loads.
ks 88c0716/p0716 electrical data 1 4 - 5 t wait v dd ext int execution of stop instruction v dddr data retention mode stop mode idle mode (oscillation stabilzation time) 0.8 v dd 0.2 v dd normal operating mode ~ ~ ~ ~ note: t wait is the same as 16 x bt clock. ~ ~ ~ ~ figure 14- 1. stop mode release timing when initiated by a n external interrupt t wait v dd reset execution of stop instruction v dddr data retention mode stop mode oscillation stabilzation time normal operating mode ~ ~ ~ ~ note: t wait is the same as 4096 x 16 x 1/f ~ ~ ~ ~ reset occurs osc . figure 14-2 . stop mode release timing when initiated by a reset
electrical data ks 88c0716/p0716 14 - 6 table 14- 4. input/output capacitance (t a = ? 40 c to + 85 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io table 14- 5. a.c. electrical characteristics (t a = ? 4 0 c to + 85 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit interrupt input high, low width t inth , t i ntl p2.4 ? p2.7 100 ? ? ns p4.0 ? p4.7 100 reset input low width t rsl input 10 ? ? m s note: user must keep the larger value with the min value . t intl t inth 0.8 v dd 0.2 v dd figure 14-3 . input timin g for external interrupts (port 2 and 4)
ks 88c0716/p0716 electrical data 1 4 - 7 reset t rsl 0.2 v dd figure 14-4 . input timing for reset table 14- 6. oscillation characteristics ( t a = ? 20 c + 85 c, v dd = 4.5 v to 5.5 v) oscillator clock circuit test condition min typ max unit crystal c2 x in x out c1 o scillation frequency 1 ? 22.1184 mhz ceramic c2 x in x out c1 o scillation frequency 1 ? 22.1184 mhz external clock x in x out x in input frequency 1 ? 22.1184 mhz
electrical data ks 88c0716/p0716 14 - 8 table 14-7 . main oscillator clock stabilization time (t st1 ) (t a = ? 20 c + 85 c, v dd = 4.5 v to 5.5 v) oscillator test condition min typ max unit crystal v dd = 4.5 v to 5.5 v ? ? 20 ms ceramic stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 10 ms note : oscillation stabilization time (t st1 ) is the time required for the cpu clock to r eturn to its normal oscillation frequency after a power-on occurs, or when stop mode is released by a reset signal. 1 mhz 4 mhz 12 mhz 2 3 4 5 6 7 1 2.7 4 .5 cpu clock v dd 5 .5 figure 14-5 . frequency vs. voltage
ks88c0716/p0716 mec hanical data mechanical data 15 - 1 15 mechanical data overview the ks88c0716 microcontroller is available in a 64-pin sdip package (64-sdip-750) and a 64-pin qfp package (64-qfp-1420f). note : dimensions are in millimeters . 64-sdip-75 0 17.00 0.2 #1 #32 #64 #33 19.05 0 - 15 0.25 +0.1 ? 0.05 1.00 0.1 0.45 0.1 57.80 0.2 58.20 max 0.51min 4.10 0.2 3.30 0.3 5.08max (1.34) 1 . 778 figure 15-1. 64-sdip-750 package dimensions
mechanical data ks88c0716/p0716 15 - 2 note : dimensions are in millimeters. 44-qfp-1010b 13.20 0.3 #44 (1.00) #1 13.20 0.3 10.00 0.2 0.35 +0.10 - 0.05 0.10 max 0.15 +0.10 - 0.05 0-8 0.05 min 2.05 0.10 2.30 max 0.80 0.20 0.80 10.00 0.2 figure 15-2. 64-qfp-1420f package dimensions
ks 88c0716/p0716 KS88P0716 otp 16- 1 16 KS88P0716 otp overview the KS88P0716 single-chip cmos microcontroller is the otp (one time programmable) version of the ks88c0716 microcontrollers. it has an on-chip eprom instead of masked rom. the eprom is accessed by serial data format. KS88P0716 is fully compatible with ks88c0716, both in function and in pin configuration. as it has simple programming requirements, KS88P0716 is ideal for use as an evaluation chip for the ks88c0716.
KS88P0716 otp ks 88c0716/p0716 16- 2 KS88P0716 64-sdip (top view) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p0.7/a15 p1.0/ad0 p1.1/ad1 p1.2/ad2 p1.3/ad3 p1.4/ad4 p1.5/ad5 p1.6/ad6 p1.7/ad7 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 v dd2 v ss2 p2.0/ as p2.1/ ds p2.2/r/ w p2.3/ dm p2.4/int0/ wait p2.5/int1 p2.6/int2 p2.7/int3 p6.7 p6.6 p6.5 p6.4 p6.3 p6.2 p6.1 p0.6/a14 p0.5/a13 p0.4/a12 p0.3/a11 p0.2/a10 p0.1/a9 p0.0/a8 p4.7/int11 p4.6/int10 p4.5/int9 p4.4/int8 p4.3/int7 p4.2/int6 sdata / p4.1/int5/tdg sclk /p4.0/int4/tcg v dd /v dd 1 v ss / v ss1 x out x in v pp /ea p5.6 p5.7 reset / reset p3.7/rxd p3.6/txd p3.5/tb p3.4/ta p3.3 p3.2 p3.1/tdck p3.0/tcck p6.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 figure 16-1. KS88P0716 pin assignments (64-sdip package)
ks 88c0716/p0716 KS88P0716 otp 16- 3 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 52 53 54 55 56 57 58 59 60 61 62 63 64 p6.7 p6.6 p6.5 p6.4 p6.3 p6.2 p6.1 p6.0 p3.0/tcck p3.1/tdck p3.2 p3.3 p3.4/ta p1.5/ad5 p1.6/ad6 p1.7/ad7 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 v dd2 v ss2 p2.0/ as p2.1/ ds p2.2/r/ w p2.3/ dm p2.4/int0/ wait p2.5/int1 p2.6/int2 p2.7/int3 p1.4/ad4 p1.3/ad3 p1.2/ad2 p1.1/ad1 p1.0/ad0 p0.7/a15 p0.6/a14 p0.5/a13 p0.4/a12 p0.3/a11 p0.2/a10 p0.1/a9 p0.0/a8 p4.7/int11 p4.6/int10 p4.5/int9 p4.4/int8 p4.3/int7 p4.2/int6 sdata / p4.1/int5/tdg sclk / p4.0/int4/tcg v dd /v dd1 v ss /v ss1 x out x in v pp /ea p5.6 p5.7 reset / reset p3.7/rxd p3.6/txd p3.5/tb KS88P0716 64-qfp (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 figure 16-2. KS88P0716 pin assignments (64-qfp package)
KS88P0716 otp ks 88c0716/p0716 16- 4 table 16-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p4.1 sdat 14 (7) i/o serial data pin (output when reading, input when writing) input and push-pull output port can be assigned. p4.0 sclk 15 (8) i serial clock pin (input only pin) ea v pp 20 (13) i eprom cell writing power supply pin (indicates otp mode entering) when writing 12.5v is applied and when reading 5 v is applied (option). reset reset 23 (9) i chip initialization v dd1 /v ss1 v dd /v ss 16/17 (9/10) i logic power supply pin. v dd should be tied to 5v during programming. note: parentheses indicate 64-qfp pin number. table 16-2. comparison of KS88P0716 and ks88c0716 features characteristic KS88P0716 ks88c0716 program memory 16 k byte eprom 16 k bytes mask rom operating voltage (v dd ) 2.7 v to 5.5 v 2.7 v to 5.5v otp programming mode v dd = 5 v, v pp (test) = 12.5v pin configuration 64 sdip, 64 qfp 64 sdip, 64 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of KS88P0716, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 15-3 below. table 16-3. operating mode selection criteria v dd vpp (test) reg/ mem address (a15-a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
ks 88c0716/p0716 KS88P0716 otp 16- 5 d.c. electrical characteristics table 16-4. d.c. electrical characteristics (t a = ? 4 0 c to + 85 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit input high voltage v ih1 all input pins except v ih2 0.8 v dd v dd v v ih2 x in v dd ? 0.5 input low voltage v il1 all input pins except v il2 0.2 v dd v v il2 x in 0.4 output high voltage v oh1 v dd = 4.5 v to 5.5 v i oh = ? 4 ma port 5 , 6 v dd ? 1.0 v v oh2 v dd = 4.5 v to 5.5 v i oh = ? 1 ma all output pins except port 5 , 6 v dd ? 1.0 output low voltage v ol1 v dd = 4.5 v to 5.5 v i ol = 15 ma ports 5 and 6 1.0 v v ol2 i ol = 2 ma ports 0 - 4 0.4
KS88P0716 otp ks 88c0716/p0716 16- 6 table 16-4 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit input high leakage current i lih1 v in = v dd all input pins except x in , x out ? ? 3 u a i lih2 v in = v dd , x in , x out 20 input low leakage current i lil1 v in = 0 v all input pins except x in , x out ? ? ? 3 u a i lil2 v in = 0 v , x in , x out ? 20 output high leakage current i loh v out = v dd all output pins ? ? 5 u a output low leakage current i lol v out = 0 v ? ? ? 5 u a pull-up resistor r l1 v in = 0 v; v dd = 5 v ports 0, 1, 4, 5 and 6 30 47 70 k w r l2 v in = 0 v; v dd = 5 v reset only 1 10 210 310 supply current (1) i dd1 (2) v dd = 5 v 10% 12 -mhz oscillation ? 12 25 ma 4 -mhz oscillation 4.5 10 v dd = 3 v 10% 12 -mhz oscillation 6 15 4 -mhz oscillation 2.5 7 i dd2 (2) idle mode; v dd = 5 v 10% 12 -mhz oscillation 2.5 6 4 -mhz oscillation 1.5 4 idle mode; v dd = 3 v 10% 12 -mhz oscillation 1.2 3 4 -mhz oscillation 0.6 1.5 i dd3 stop mode: v dd = 5 v 10% 0.1 3 ua note s : 1. supply current does not include current drawn through internal pull-up resistors or external output current loads. 2. at supply current, the cpu clock frequency is the same as oscillation frequency (cpu use non divided clock).
ks 88c0716/p0716 KS88P0716 otp 16- 7 start address= first location v dd =5v, v pp =12.5v x = 0 program one 1ms pulse increment x x = 10 verify 1 byte last address v dd = v pp = 5 v compare all byte device passed increment address verify byte device failed pass fail no fail yes fail no figure 16-3. otp programming algorithm
KS88P0716 otp ks 88c0716/p0716 16- 8 notes

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